Current research is directed towards a greater density of active components per unit area of semiconductor substrate, effective isolation between circuits must be installed properly to avoid the short circuit of adjacent components. There are thermal techniques, such as the local oxidation of silicon (LOCOS), to grow silicon dioxide layers with a thickness more than one thousand angstroms between active devices. The insulating characteristic of silicon dioxide is for isolation purposes and is also called field oxide.
As the size of integrated circuits is reduced, the devices that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical chip. Conventional isolation of circuit components in modern integrated circuit technology takes the form of shallow trenches which are etched into the semiconductor substrate and are filled with an insulating material such as silicon dioxide. These areas are generally referred to as shallow trench isolation (STI). In sub 0.5 micron applications, the use of shallow trench isolation between devices in an integrated circuit wafer is frequently used in place of the LOCOS process. Shallow trench isolation regions serve to isolate the active regions of the integrated circuit and, typically vary widely in dimensions because the active regions of the integrated circuit can be of virtually any size.
In the advanced semiconductor processes, a complex topography of integrated circuits are often encountered. Due to this reason, a problem always occurs in achieving a uniform shallow trench isolation oxide fill, especially when shallow trenches of widely varying widths are used. In order to solve the problem, a number of methods have been developed for filling shallow trench isolation with insulating materials and for planarizing the topography.
The filling methods of STI include chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD), which take advantage of the fact that material can be evaporated as a vapor and deposited on a surface. PECVD can further improve the stress of the deposited film and reduce the wafer warpage or peeling by the ion bombardment. Planarization methods such as resist etch back (REB) process, reactive ion etching (RIE) process, spin on glass (SOG) method, and chemical mechanical polishing (CMP) procedure are employed, alone or in combination, to planarize the surface of the semiconductor substrate.
Conventional shallow trench isolation process is strongly dependent on the controllability of chemical mechanical polishing (CMP), which is the only one method to provide the global planarization of ultra-large semiconductor integration (ULSI) processes. After the oxide-filled shallow trench isolation is formed, many attempts have been made using CMP processes. One such method is described in U.S. Pat. No. 5,494,857, entitled "CHEMICAL MECHANICAL PLANARIZATION OF SHALLOW TRENCHES IN SEMICONDUCTOR SUBSTRATES" by S. S. Cooperman et al., which apply CMP techniques to etch back the insulating layers and form shallow trench isolation.
Another method is described in U.S. Pat. No. 5,312,512, entitled "GLOBAL PLANARIZATION USING SOG AND CMP" by Allman, which discuss the global planarization of integrated circuit wafers using Spin On Glass and Chemical Mechanical Polishing processes.
Nevertheless, a plurality of factors include polishing slurry, pressure on the wafer, polishing pad, particle size distribution of slurry . . . , etc., will affect the CMP planarization profile. A serious drawback for CMP is the difficulty in end point detection. The other weak points induced from CMP include: easy to form microscratches on the polishing surface, bad within wafer uniformity, pattern-dependent polishing uniformity, instability of polishing rate, and contamination control of the wafer.
According to the above descriptions, although CMP can achieve true global planarization on the deposited film, the strong dependence upon CMP of shallow trench isolation may complicate the processes and cause some problems that are not easy to solve.